Renesas SH7781 - Manual (Page 700)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 670 of 1658
REJ09B0261-0100
Channel Name Abbrev. R/W P4 Address
Area 7
Address
Access
Size* 3
Sync
clock
6 to 11 DMA operation register 1 DMAOR1 R/W* 2 H'FCC0 8060 H'1CC0 8060 16 Bck, Pck* 5
10 DMA source address register 10 SAR10 R/W H'FCC0 8070 H'1CC0 8070 32 Bck
DMA destination address register 10 DAR10 R/W H'FCC0 8074 H'1CC0 8074 32 Bck
DMA transfer count register 10 TCR10 R/W H'FCC0 8078 H'1CC0 8078 32 Bck
DMA channel control register 10 CHCR10 R/W* 1 H'FCC0 807C H'1CC0 807C 32 Bck, Pck* 4
11 DMA source address register 11 SAR11 R/W H'FCC0 8080 H'1CC0 8080 32 Bck
DMA destination address register 11 DAR11 R/W H'FCC0 8084 H'1CC0 8084 32 Bck
DMA transfer count register 11 TCR11 R/W H'FCC0 8088 H'1CC0 8088 32 Bck
DMA channel control register 11 CHCR11 R/W* 1 H'FCC0 808C H'1CC0 808C 32 Bck, Pck* 4
6 DMA source address register B6 SARB6 R/W H'FCC0 8120 H'1CC0 8120 32 Bck
DMA destination address register B6 DARB6 R/W H'FCC0 8124 H'1CC0 8124 32 Bck
DMA transfer count register B6 TCRB6 R/W H'FCC0 8128 H'1CC0 8128 32 Bck
7 DMA source address register B7 SARB7 R/W H'FCC0 8130 H'1CC0 8130 32 Bck
DMA destination address register B7 DARB7 R/W H'FCC0 8134 H'1CC0 8134 32 Bck
DMA transfer count register B7 TCRB7 R/W H'FCC0 8138 H'1CC0 8138 32 Bck
8 DMA source address register B8 SARB8 R/W H'FCC0 8140 H'1CC0 8140 32 Bck
DMA destination address register B8 DARB8 R/W H'FCC0 8144 H'1CC0 8144 32 Bck
DMA transfer count register B8 TCRB8 R/W H'FCC0 8148 H'1CC0 8148 32 Bck
9 DMA source address register B9 SARB9 R/W H'FCC0 8150 H'1CC0 8150 32 Bck
DMA destination address register B9 DARB9 R/W H'FCC0 8154 H'1CC0 8154 32 Bck
DMA transfer count register B9 TCRB9 R/W H'FCC0 8158 H'1CC0 8158 32 Bck
6, 7 DMA extended resource selector 3 DMARS3 R/W H'FCC0 9000 H'1CC0 9000 16 Pck
8, 9 DMA extended resource selector 4 DMARS4 R/W H'FCC0 9004 H'1CC0 9004 16 Pck
10, 11 DMA extended resource selector 5 DMARS5 R/W H'FCC0 9008 H'1CC0 9008 16 Pck
Notes: 1. To clear the flag, the HE and TE bits in CHCR can be read as 1, and then, 0 can be
written to.
2. To clear the flag, the AE and NMIF bits in DMAOR can be read as 1, and then, 0 can be
written to.
3. Accessing with other access sizes is prohibited.
4. The synchronous clock for the HE and TE bits in CHCR is Bck, and the synchronous
clock for the other bits in CHCR is Pck.
5. The synchronous clock for the AE, NMIF, and DME bits in DMAOR is Bck, and the
synchronous clock for the CMS and PR bits in DMAOR is Pck.