Renesas SH7781 - Manual (Page 874)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 844 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Internal
Update Description
7, 6 TVM 10 R/W None TV Synchronization Mode
00: Master mode
HSYNC, VSYNC, CSYNC are output
01: Synchronization method switching mode
When switching from TV sync mode to
master mode, or from master mode to TV
sync mode, is necessary, the switching
should pass through this mode. In this
mode, operation of the display system is
forcibly halted, and DISP outputs a low level
signal. Clock signal supply to the DCLKIN
pin can also be halted (input disabled)
(within the LSI the level is fixed high).
When a clock signal is supplied to the
DCLKIN pin, the clock is output from the
DCLKOUT pin.
The
HSYNC pin is the EXHSYNC input, the
VSYNC pin is the EXVSYNC input, and the
ODDF pin is the ODDF input.
However, when the ODPM bit in DSMR is 1,
the ODDF pin output is clamped.
10: TV synchronization mode
The
HSYNC pin is the EXHSYNC input, the
VSYNC pin is the EXVSYNC input, and the
ODDF pin is the ODDF input.
However, when the ODPM bit in DSMR is 1,
the ODDF pin output is clamped.
11: Setting prohibited
5, 4 SCM 00 R/W None Scan Mode
00: Non-interlace mode
01: Setting prohibited
10: Interlace sync mode
11: Interlace sync and video mode
3 to 0
⎯ All
0 R None Reserved
These bits are always read as 0. The write value
should always be 0.