Renesas SH7781 - Manual (Page 732)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 702 of 1658
REJ09B0261-0100
Choose whether DREQ is detected by edge or level with the DREQ level (DL) bit and DREQ
select (DS) bit in CHCR0 to CHCR3 shown in table 14.5. The source of the transfer request does
not have to be the transfer source or transfer destination.
Table 14.5 External Request Detection Selection with DL and DS Bits
CHCR
DL DS Detection of External Request
0 0 Low level detection (initial value:
DREQ)
1 Falling edge detection
1 0 High level detection
1 Rising edge detection
When DREQ is accepted, the DREQ pin cannot accept requests. After acknowledge DACK is
output to the accepted DREQ, the DREQ pin can accept requests again.
When DREQ is used for level detection, the timing to detect the next DREQ after outputting
DACK depends on the DO bit in CHCR.
For details, see section 14.4.7, DREQ Pin Sampling Timing.
Table 14.6 Selecting External Request Detection with the DO Bit
CHCR
DO External Request
0 Overrun 0 (initial value)
1 Overrun 1
DACK can be output to only LBSC space, and is output at the same timing as
CSn. The setting
whether DACK is output during the reading or writing cycle is selected by the AM bit in CHCR
shown in table 14.7.
Table 14.7 Acknowledge Mode Selection with AM Bit
CHCR
AM External Request
0 DACK output during the reading cycle (initial value)
1 DACK output during the writing cycle