Renesas SH7781 - Manual (Page 303)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 273 of 1658
REJ09B0261-0100
10.3 Register Descriptions
Table 10.3 shows the INTC register configuration. Table 10.4 shows the register states in each
operating mode.
Table 10.3 INTC Register Configuration
Name Abbreviation R/W P4 Address Area 7 Address
Access
Size Sync.
Clock
Interrupt control register 0 ICR0 R/W H'FFD0 0000 H'1FD0 0000 32 Pck
Interrupt control register 1 ICR1 R/W H'FFD0 001C H'1FD0 001C 32 Pck
Interrupt priority register INTPRI R/W H'FFD0 0010 H'1FD0 0010 32 Pck
Interrupt source register INTREQ R/(W)* 1 H'FFD0 0024 H'1FD0 0024 32 Pck
Interrupt mask register 0 INTMSK0 R/W H'FFD0 0044 H'1FD0 0044 32 Pck
Interrupt mask register 1 INTMSK1 R/W H'FFD0 0048 H'1FD0 0048 32 Pck
Interrupt mask register 2 INTMSK2 R/W H'FFD4 0080 H'1FD4 0080 32 Pck
Interrupt mask clear register 0 INTMSKCLR0 R/W H'FFD0 0064 H'1FD0 0064 32 Pck
Interrupt mask clear register 1 INTMSKCLR1 R/W H'FFD0 0068 H'1FD0 0068 32 Pck
Interrupt mask clear register 2 INTMSKCLR2 R/W H'FFD4 0084 H'1FD4 0084 32 Pck
NMI flag control register NMIFCR R/(W)* 2 H'FFD0 00C0 H'1FD0 00C0 32 Pck
User interrupt mask level
register USERIMASK R/W H'FFD3 0000 H'1FD3 0000 32 Pck
INT2PRI0 R/W H'FFD4 0000 H'1FD4 0000 32 Pck
INT2PRI1 R/W H'FFD4 0004 H'1FD4 0004 32 Pck
Interrupt priority registers
INT2PRI2 R/W H'FFD4 0008 H'1FD4 0008 32 Pck
INT2PRI3 R/W H'FFD4 000C H'1FD4 000C 32 Pck
INT2PRI4 R/W H'FFD4 0010 H'1FD4 0010 32 Pck
INT2PRI5 R/W H'FFD4 0014 H'1FD4 0014 32 Pck
INT2PRI6 R/W H'FFD4 0018 H'1FD4 0018 32 Pck
INT2PRI7 R/W H'FFD4 001C H'1FD4 001C 32 Pck
INT2PRI8 R/W H'FFD4 0020 H'1FD4 0020 32 Pck
INT2PRI9 R/W H'FFD4 0024 H'1FD4 0024 32 Pck
Interrupt source register (not
affected by the mask state) INT2A0 R H'FFD4 0030 H'1FD4 0030 32 Pck