Renesas SH7781 - Manual (Page 237)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 207 of 1658
REJ09B0261-0100
7.9 32-Bit Boot Function
The address mode of this LSI after a power-on reset or manual reset can be switched between 29-
bit address mode and 32-bit address extended mode by specifying external pins. The following
changes apply when this LSI is booted up in 32-bit address extended mode.
7.9.1 Initial Entries to PMB
When 32-bit address extended mode is specified by external pins, the following initial entries are
recorded in the PMB after a power-on reset or manual reset, and the SE bit in the PASCR register
is initialized to 1. For entries 2 to 15, only the V bit is initialized to 0.
Entry VPN[31:24] PPN[31:24] V SZ[1:0] C UB WT
0 10000000 00000000 1 11 1 0 1
1 10100000 00000000 1 11 0 0 0
7.9.2 Notes on 32-Bit Boot
Immediately after a power-on or manual reset, the P1 or P2 area is mapped to the PMB. Therefore,
when an area other than that indicated by the initial entry needs to be mapped, follow the
procedures below to modify the PMB, taking care not to generate PMB misses and multiple PMB
hits. The procedure should be set up within the boot routine and should be executed before
activation of the caches and TLB (CCR.ICE
= 1, CCR.OCE = 1, and MMUCR.AT = 1). Do not
use routines other than the boot routine to change the value recorded in the PMB.
(1)
When the Program Modifying the PMB is in the P1 or P2 Area
1. Read the initial entry, change only the SZ bits to reduce the page size, and save the new value
over the previous entry. The program that changes the PMB should be allocated within 1
Mbyte of the top of the page with the reduced size.
2. Invalidate the entry remaining in the ITLB that corresponds to the PMB by writing 1 to the TI
bit in the MMUCR register.
3. In the memory-mapped PMB, record PMB entries to fill the P1 or P2 area in which the PMB
translation information is evicted by step 1.
4. Execute one of the following steps, A, B, and C. Do not execute a branch or operand access for
the P1 or P2 area in which the PMB translation information is evicted by step 1.
A. Perform a branch using the RTE instruction.
B. Execute the ICBI instruction for any address (including non-cacheable area).