Renesas SH7781 - Manual (Page 624)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 594 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
19 to 1
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
0 MBARE 0 SH: R/W
PCI: R
PCI Memory Base Address Register 0 Enable
Enables accesses to the local address space 0 by
setting this bit to 1.
0: MBAR0 disabled
1: MBAR0 enabled
(3)
PCI Local Space Register 1 (PCILSR1)
See section 13.4.4 (1), Accessing Memory Space in This LSI.
SH R/W:
PCI R/W:
R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R
R R R R R R R R R R R R R R R R
SH R/W:
PCI R/W:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — LSR — — —
Bit:
Initial value:
R/W R R R R R R R R R R R R R R R
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MBA
RE
— — — — — — — — — — — — — — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Description
31 to 29
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.