Renesas SH7781 - Manual (Page 309)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 279 of 1658
REJ09B0261-0100
Bit Name
Initial
Value R/W
Description
21 LVLMODE 0 R/W Level-sense IRQ/
IRL with holding function
Selects whether or not to use the holding function for
level-sense IRQ and IRL interrupts.
0: Level-sense IRQ and IRL interrupt requests are held
(initial value)
1: Level-sense IRQ and IRL interrupt requests are not
held
Rewriting to this bit should be performed by the
initialization routine before canceling the masking
(INTMASK0 and INTMASK1) for the IRQ interrupts and
IRL interrupt. After this, do not rewrite this bit until
power-on reset or manual reset is made. The initial
value is 0, however. it is recommended to use INTC
after this bit has been set to 1 by the initialization
routine.
For the details of the operation when this bit is set to 0,
refer to section 10.4.2, IRQ Interrupts, section 10.4.3,
IRL Interrupts, section 10.7.1, Example of Handing
Routine of IRL Interrupts and Level Detection IRQ
Interrupts when ICR0.LVLMODE = 0, and section
10.7.3, Clearing IRQ and IRL Interrupt Requests.
20 to 0
⎯ All
0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Notes: 1. When IRLM0 and IRLM1 are changed from 0 to 1, the IRL interrupt source that has
been detected or held is cleared. When IRLM0 and IRLM1 are changed from 1 to 0, the
IRL interrupt source that has been detected or held is not cleared.
2. When using the IRQ/
IRL3 to IRQ/IRL0 pins or IRQ/IRL7 to IRQ/IRL4 pins as encoded
IRL interrupt inputs, set IM00 to IM03 or IM04 to IM07 of the interrupt mask register 0 to
1, respectively.