Renesas SH7781 - Manual (Page 495)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 465 of 1658
REJ09B0261-0100
12.3 Data Alignment
The DBSC2 accesses DDR2-SDRAM with a fixed burst length of 4 (figure 12.2). As shown in
table 12.3 and table 12.4, invalid read data is discarded during reading, and data mask signals are
used to mask invalid data during writing, according to the access size. The access times in tables
12.3 and 12.4 correspond to the burst times during reading/writing shown in figure 12.2. For
example, when the external bus width is 32 bits with a little endian, the second access (falling
edge of DQS) includes valid data if a byte access of address (8n
+ 0, 1, 2, 3) occurs.
Tables 12.5 to 12.8 show the correspondence with data on the external data bus for each access
size. During 16-byte and 32-byte accesses, quad word (8 bytes) access is combined, and the
SDRAM command is issued the necessary number of times according to the size to access the
SDRAM as shown in figures 12.3 and 12.4. The DDR2-SDRAM specification stipulates
sequential address changes (0
→1→2→3, 1→2→3→0, 2→3→0→1, 3→0→1→2), so that the
address provided as a command is different for reading and for writing. Endian switching is
performed at power-on reset by switching using external pin MODE8.