Renesas SH7781 - Manual (Page 563)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 533 of 1658
REJ09B0261-0100
MCK0,
MCK1
MA[14:11]
MA[9:0]
MBA[2:0]
MCKE
MCS
MRAS
MCAS
MWE
MA[10]
ACT
bank A bank A
Invalid
Invalid
Invalid
Invalid
MDQS[3:0]
MDQ[31:0]
MDM[3:0]
Invalid Invalid
SDRAM
command
Invalid
Invalid
Invalid Invalid
Valid
Valid
Valid
Valid
Valid
Valid
High level
Example of CL = 3
Write data
WRITE
Figure 12.10 Waveforms for 1/2/4/8/16-Byte Writing
(When the Bus Width Is Set to 32 Bits)
Figure 12.11 shows waveforms for 32-byte writing when the bus width is set to 32 bits. In this
case, the WRITE command is issued twice. In this example, write access processing is executed
for bank A after the ACT command is issued, but when there is a page hit, access begins with the
issue of the WRITE command.