Renesas SH7781 - Manual (Page 168)

6. Floating-Point Unit (FPU)
Rev.1.00 Jan. 10, 2008 Page 138 of 1658
REJ09B0261-0100
6.5 Floating-Point Exceptions
6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions
FPU-related exceptions are occurred when an FPU instruction is executed with SR.FD set to 1.
When the FPU instruction is in other than delayed slot, the general FPU disable exception is
occurred. When the FPU instruction is in the delay slot, the slot FPU disable exception is
occurred.
6.5.2 FPU Exception Sources
The exception sources are as follows:
• FPU error (E): When FPSCR.DN = 0 and a denormalized number is input
• Invalid operation (V): In case of an invalid operation, such as NaN input
• Division by zero (Z): Division with a zero divisor
• Overflow (O): When the operation result overflows
• Underflow (U): When the operation result underflows
• Inexact exception (I): When overflow, underflow, or rounding occurs
The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E, V,
Z, O, U, and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding
to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled.
When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set to 1,
and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU exception
does not occur, the corresponding bit in the FPU exception cause field is cleared to 0, but the
corresponding bit in the FPU exception flag field remains unchanged.