Renesas SH7781 - Manual (Page 718)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 688 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Descriptions
2 IE 0 R/W Interrupt Enable
Specifies whether an interrupt request is generated to
the CPU at the end of the final DMA transfer. Setting
this bit to 1 generates an interrupt request (DMINT) to
the CPU when the TE bit is set to 1 and a read cycle of
the final DMA transfer has ended. To confirm that the
final transfer has ended, execute a dummy read of the
destination space after issuing the SYNCO instruction.
0: Interrupt request disabled
1: Interrupt request enabled
1 TE 0 R/(W)* Transfer End Flag
The TE bit is set to 1 when DMA transfer count register
(TCR) is set to 0 (when the DMAC starts executing the
final DMA transfer). The TE bit is not set, if DMA
transfer ends due to an NMI interrupt or DMA address
error before TCR is cleared to 0, or if DMA transfer is
ended by clearing the DE bit and DME bit in DMA
operation register (DMAOR). To clear the TE bit, the TE
bit should be read as 1, and then, 0 is written to.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: When DMA transfer is being performed or DMA
transfer has been interrupted
[Clearing condition]: Write 0 after TE is read as 1
1: TCR = 0 (when the final DMA transfer is being
performed or the DMA transfer ends)
0 DE 0 R/W DMA Enable
Enables or disables DMA transfer.
In auto-request mode, DMA transfer starts by setting
the DE bit and the DME bit in DMAOR to 1. The TE,
NMIF, and AE bits in DMAOR should be 0.
In an external request or on-chip peripheral module
request, DMA transfer starts if DMA transfer request is
generated by the corresponding devices or
corresponding peripheral modules after the DE and
DME bits are set to 1. In this case, too, the TE, NMIF,
and AE bits should be 0.
Clearing the DE bit to 0 can abort DMA transfer.
In an on-chip peripheral module request, when aborting
a transfer by clearing the DE bit, clear the DE bit while
the transfer request has been cleared.
0: DMA transfer disabled
1: DMA transfer enabled
Note: * To clear the flag, 0 can be written to.