Renesas SH7781 - Manual (Page 1483)

29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1453 of 1658
REJ09B0261-0100
Section 29 User Break Controller (UBC)
The user break controller (UBC) provides versatile functions to facilitate program debugging.
These functions help to ease creation of a self-monitor/debugger, which allows easy program
debugging using this LSI alone, without using the in-circuit emulator. Various break conditions
can be set in the UBC: instruction fetch or read/write access of an operand, operand size, data
contents, address value, and program stop timing for instruction fetch.
29.1 Features
1. The following break conditions can be set.
Break channels: Two (channels 0 and 1)
User break conditions can be set independently for channels 0 and 1, and can also be set as a
single sequential condition for the two channels, that is, a sequential break. (Sequential break
involves two cases such that the channel 0 break condition is satisfied in a certain bus cycle
and then the channel 1 break condition is satisfied in a different bus cycle, and vice versa.)
• Address
When 40 bits containing ASID and 32-bit address are compared with the specified value, all
the ASID bits can be compared or masked.
32-bit address can be masked bit by bit, allowing the user to mask the address in desired page
sizes such as lower 12 bits (4-Kbyte page) and lower 10 bits (1-Kbyte page).
• Data
32 bits can be masked only for channel 1.
• Bus cycle
The program can break either for instruction fetch (PC break) or operand access.
• Read or write access
• Operand sizes
Byte, word, longword, and quadword are supported.
2. The user-designated exception handling routine for the user break condition can be executed.
3. Pre-instruction-execution or post-instruction-execution can be selected as the PC break timing.
4. A maximum of 2 12 – 1 repetition counts can be specified as the break condition (available only
for channel 1).