Renesas SH7781 - Manual (Page 461)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 431 of 1658
REJ09B0261-0100
Tm1
CLKOUT
A
RD/FRAME
CSn
R/ W
D63 to D0
BS
Tmd1
RDY
DACKn
D0
In this example, DACKn is active-high. The circle indicates the sampling timing.
Figure 11.26 MPX Interface Timing 3
(Single Write Cycle, IW
= 0000, No External Wait, 64-Bit Bus Width)