Renesas SH7781 - Manual (Page 24)

Rev.1.00 Jan. 10, 2008 Page xxiv of xxx
REJ09B0261-0100
23.2 Input/Output Pins............................................................................................................. 1153
23.3 Register Descriptions ....................................................................................................... 1153
23.3.1 Control Register (SPCR) .................................................................................. 1155
23.3.2 Status Register (SPSR) ..................................................................................... 1158
23.3.3 System Control Register (SPSCR) ................................................................... 1161
23.3.4 Transmit Buffer Register (SPTBR) .................................................................. 1163
23.3.5 Receive Buffer Register (SPRBR).................................................................... 1164
23.4 Operation ......................................................................................................................... 1165
23.4.1 Operation Overview with FIFO Mode Disabled............................................... 1165
23.4.2 Operation with FIFO Mode Enabled ................................................................ 1166
23.4.3 Timing Diagrams .............................................................................................. 1167
23.4.4 HSPI Software Reset ........................................................................................ 1169
23.4.5 Clock Polarity and Transmit Control................................................................ 1169
23.4.6 Transmit and Receive Routines ........................................................................ 1169
23.4.7 Flags and Interrupt Timing ............................................................................... 1170
23.4.8 Low-Power Consumption and Clock Synchronization..................................... 1170
Section 24 Multimedia Card Interface (MMCIF) ..................................................... 1171
24.1 Features............................................................................................................................ 1171
24.2 Input/Output Pins............................................................................................................. 1172
24.3 Register Descriptions ....................................................................................................... 1173
24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5)............................................ 1177
24.3.2 Command Start Register (CMDSTRT) ............................................................ 1178
24.3.3 Operation Control Register (OPCR)................................................................. 1179
24.3.4 Card Status Register (CSTR)............................................................................ 1181
24.3.5 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2)................................. 1183
24.3.6 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2) ............................... 1187
24.3.7 Transfer Clock Control Register (CLKON) ..................................................... 1193
24.3.8 Command Timeout Control Register (CTOCR)............................................... 1194
24.3.9 Transfer Byte Number Count Register (TBCR) ............................................... 1195
24.3.10 Mode Register (MODER)................................................................................. 1196
24.3.11 Command Type Register (CMDTYR).............................................................. 1197
24.3.12 Response Type Register (RSPTYR)................................................................. 1198
24.3.13 Transfer Block Number Counter (TBNCR) ..................................................... 1202
24.3.14 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD).......................... 1203
24.3.15 Data Timeout Register (DTOUTR) .................................................................. 1205
24.3.16 Data Register (DR) ........................................................................................... 1206
24.3.17 FIFO Pointer Clear Register (FIFOCLR) ......................................................... 1207
24.3.18 DMA Control Register (DMACR) ................................................................... 1208
24.4 Operation ......................................................................................................................... 1209