Renesas SH7781 - Manual (Page 653)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 623 of 1658
REJ09B0261-0100
(23) PCI I/O Bank Mask Register (PCIIOBMR)
This register is the mask register for PCIIOBR. This register specifies the I/O space size on the
PCI bus for an I/O-read or I/O-write to the PCI I/O space by the CPU or DMAC.
See section 13.4.3 (3), Accessing PCI I/O Space.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — —
R R R R R R R R R R R R
R R R/W R/W R/W R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — —
— — — — — — — — — — — — — — — —
— — — — — — — — — — — — — — — —
— — — — — — — — — — — — — IOBAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Description
31 to 21 — All 0 SH: R
PCI:
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
20 to 18 IOBAM All 0 SH: R/W
PCI:
⎯
PCI I/O Space Bank Address Mask (3 bits)
000: 256 kbytes
001: 512 kbytes
011: 1 Mbyte
111: 2 Mbytes
Other than above: Setting prohibited
17 to 0
⎯
All 0 SH: R
PCI:
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.