2 queue address control register 0 (qacr0) – Renesas SH7781 User Manual
Page 248
8. Caches
Rev.1.00 Jan. 10, 2008 Page 218 of 1658
REJ09B0261-0100
8.2.2
Queue Address Control Register 0 (QACR0)
QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is disabled.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit:
Initial value:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R
R
R/W:
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AREA0
Bit Bit
Name
Initial
Value R/W
Description
31 to 5
⎯ All
0
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
4 to 2
AREA0
Undefined R/W
When the MMU is disabled, these bits generate
physical address bits [28:26] for SQ0.
1, 0
⎯ All
0
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.