Renesas SH7781 - Manual (Page 491)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 461 of 1658
REJ09B0261-0100
The frequency of the SDRAM operation clocks MCK0,
MCK0, MCK1, and MCK1 is the same as
the frequency of the DDR clock.
MDQ7 to MDQ0 correspond to MDQS0 and MDM0, MDQ15 to MDQ8 correspond to MDQS1
and MDM1, MDQ23 to MDQ16 correspond to MDQS2 and MDM2, and MDQ31 to MDQ24
correspond to MDQS3 and MDM3. When the external data bus width is 16 bits, MDQ15 to
MDQ0 are used.
Table 12.2 shows an example of connections when a total of four 2-Gb DDR2-SDRAM units
(256M
× 8 bits) are used, with the external data bus width set to 32 bits. Command-related signals
(MCKE,
MWE, MCS, MRAS, MCAS, MA14- MA0, MBA2- MBA0) are connected in common
to four DDR2-SDRAM units. Data signals (MDQ31 to MDQ0, MDQS3 to MDQS0,
MDQS3 to
MDQS0, and MDM3 to MDM0) are connected to memory in 8-bit units. Clocks MCK1 and
MCK1 are connected to DDR2-SDRAM corresponding to the data signal upper sides (MDQ31 to
MDQ16, MDQS3, MDQS2,
MDQS3, MDQS2, MDM3, and MDM2), and MCK0 and MCK0 are
connected to DDR2-SDRAM corresponding to the lower sides (MDQ15 to MDQ0, MDQS1,
MDQS0,
MDQS1, MDQS0, MDM1, and MDM0). Address pins MA14 to MA0 should be
connected to the DDR2-SDRAM address pins, without swapping the order.
Nothing should be connected to unused pins.