Renesas SH7781 - Manual (Page 709)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 679 of 1658
REJ09B0261-0100
14.3.5 DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11)
TCR are 32-bit readable/writable registers that specify the DMA transfer count. When the value is
set to H'00000001, H'00FFFFFF, H'00000000, the transfer count is 1, 16,777,215, and 16,777,216
(the maximum) respectively. During a DMA transfer, these registers indicate the remaining
transfer count.
The upper eight bits in TCR (bits 31 to 24) are always read as 0. The write value should always be
0.
The initial value of TCR is undefined.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W: