10 hac control register (hacacr) – Renesas SH7781 User Manual
Page 1314
25. Audio Codec Interface (HAC)
Rev.1.00 Jan. 10, 2008 Page 1284 of 1658
REJ09B0261-0100
25.3.10
HAC Control Register (HACACR)
HACACR is a 32-bit read/write register used for controlling the HAC interface.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Bit:
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Initial value:
R
R/W
R/W
R
R
R/W
R
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W:
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
⎯
⎯
⎯
⎯
⎯
⎯
TX12_
ATOMIC
RXDMAL
_EN
TXDMAL
_EN
RXDMAR
_EN
TXDMAR
_EN
DMA
RX16
DMA
TX16
0
Bit Bit
Name
Initial
Value R/W Description
31
⎯ 1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
30
DMARX16 0
R/W
16-bit RX DMA Enable
0: Disables 16-bit packed RX DMA mode. Enables the
RXDMAL_EN and RXDMAR_EN settings.
1: Enables 16-bit packed RX DMA mode. Disables the
RXDMAL_EN and RXDMAR_EN settings.
29
DMATX16
0
R/W
16-bit TX DMA Enable
0: Disables 16-bit packed TX DMA mode. Enables the
TXDMAL_EN and TXDMAR_EN settings.
1: Enables 16-bit packed TX DMA mode. Disables the
TXDMAL_EN and TXDMAR_EN settings.
28, 27
⎯ All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
26
TX12_ATOMIC
1
R/W
TX Slot 1 and 2 Atomic Control
0: Transmits TX data in HACCSAR and that in
HACCSDR separately. (Setting prohibited)
1: Transmits TX data in HACCSAR and that in
HACCSDR in the same frame if bit 19 in HACCSAR
is 0 (write). (HACCSAR must be written last.)