Renesas SH7781 - Manual (Page 1192)

23. Serial Peripheral Interface (HSPI)
Rev.1.00 Jan. 10, 2008 Page 1162 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
8 FFEN 0 R/W FIFO Mode Enable
Enables or disables the FIFO mode. When FIFO mode
is enabled, two 8-entry FIFOs are made available, one
for transmit data and one for receive data. These FIFOs
are read and written via SPTBR and SPRBR,
respectively. When FIFO mode is disabled, the SPTBR
and SPRBR are used directly so new data must be
written to SPTBR and read from SPRBR for each and
every transfer through the HSPI bus. FIFO mode must
be disabled if DMA requests are also to be used to
service SPTBR and SPRBR.
0: FIFO mode disabled
1: FIFO mode enabled
7 LMSB 0 R/W LSB/MSB First Control
0: Data is transmitted and received most significant bit
(MSB) first.
1: Data is transmitted and received least significant bit
(LSB) first.
6 CSV 1 R/W Chip Select Value
Controls the value output as the chip select signal when
the HSPI is a master and manual generation of the chip
select signal has been selected.
0: Chip select output is low.
1: Chip select output is high.
5 CSA 0 R/W Automatic/Manual Chip Select
0: Chip select output is automatically generated during
data transfer.
1: Chip select output is manually controlled, with its
value being determined by the CSV bit.
4 TFIE 0 R/W Transmit Complete Interrupt Enable
0: Transmit complete interrupt disabled
1: Transmit complete interrupt enabled
3 ROIE 0 R/W Receive Overrun Occurred/Warning Interrupt Enable
0: Receive overrun occurred/warning interrupt disabled
1: Receive overrun occurred/warning interrupt enabled