Renesas SH7781 - Manual (Page 275)

9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 245 of 1658
REJ09B0261-0100
The CPU can access the P4 area in the virtual address space (when SR.MD
= 1) or on-chip
memory area (when SR.MD
= 0 and RAMCR.RMD = 1). Access operations involving these
addresses are always non-cacheable.
Table 9.3 U Memory Addresses
Address Space Memory Address
Virtual address H'E55F 0000 to H'E560 FFFF
Physical address H'E55F 0000 to H'E560 FFFF
• Ports
The U memory has three independent read/write ports and is connected to the operand bus, the
cache/RAM internal bus, and the SuperHyway bus. The operand bus is used when the U
memory is accessed through operand read access. The cache/RAM internal bus is used when
the U memory is accessed through instruction fetch and operand write access. The
SuperHyway bus is used for U memory access from the SuperHyway bus master module.
• Priority
In the event of simultaneous accesses to the U memory from different buses, the access
requests are processed according to priority. The priority order is: SuperHyway bus >
cache/RAM internal bus > operand bus.