Renesas SH7781 - Manual (Page 197)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 167 of 1658
REJ09B0261-0100
7.3.2 Instruction TLB (ITLB) Configuration
The ITLB is used to translate a virtual address to a physical address in an instruction access.
Information in the address translation table located in the UTLB is cached into the ITLB. Figure
7.8 shows the ITLB configuration. The ITLB consists of four fully-associative type entries.
PPN[28:10]
PPN[28:10]
PPN[28:10]
PPN[28:10]
SZ[1:0]
SZ[1:0]
SZ[1:0]
SZ[1:0]
SH
SH
SH
SH
C
C
C
C
PR
PR
PR
PR
ASID[7:0]
ASID[7:0]
ASID[7:0]
ASID[7:0]
VPN[31:10]
VPN[31:10]
VPN[31:10]
VPN[31:10]
V
V
V
V
Entry 0
Entry 1
Entry 2
Entry 3
Notes: 1. The D and WT bits are not supported.
2. There is only one PR bit, corresponding to the upper bit of the PR bits in the UTLB.
Figure 7.8 ITLB Configuration (TLB Compatible Mode)
7.3.3 Address Translation Method
Figure 7.9 shows a flowchart of a memory access using the UTLB.