Renesas SH7781 User Manual
Page 1508
29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1478 of 1658
REJ09B0261-0100
• When the match condition is satisfied at the instruction fetch cycle for the first channel in the
sequence whereas the match condition is satisfied at the operand access cycle for the second
channel in the sequence:
Instruction B is 0 or one instruction after
instruction A
Sequential operation is not guaranteed.
Instruction B is two or more instructions after
instruction A
Sequential operation is guaranteed.
• When the match condition is satisfied at the operand access cycle for the first channel in the
sequence whereas the match condition is satisfied at the instruction fetch cycle for the second
channel in the sequence:
Instruction B is 0 to five instructions after
instruction A
Sequential operation is not guaranteed.
Instruction B is six or more instructions after
instruction A
Sequential operation is guaranteed.
• When the match condition is satisfied at the operand access cycle for both the first and second
channels in the sequence:
Instruction B is 0 to five instructions after
instruction A
Sequential operation is not guaranteed.
Instruction B is six or more instructions after
instruction A
Sequential operation is guaranteed.