Renesas SH7781 - Manual (Page 1616)

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1586 of 1658
REJ09B0261-0100
Tm1 Tmd1w Tmd1 Tm0 Tmd1w Tmd1 Tmd1w
CLKOUT
RD/FRAME
RD/ WR
WEn
RDY
BS
D31 to D0
CSn
DACKn
(DA)
t
FMD
t
FMD
t
BSD
t
BSD
t
BSD
t
BSD
t
CSD
t
CSD
t
DACD
t
RDH
t
RDS
D0
t
RDYH
t
RDYS
t
DACD
t
RWD
t
RWD
t
WED1
t
WED1
t
FMD
t
FMD
t
CSD
t
CSD
t
RDH
t
RDS
t
WDD
t
WDD
t
WDD
A D0 A
t
WDD
t
RWD
t
RWD
t
WED1
t
WED1
t
DACD
t
DACD
t
RDYH
t
RDYS
tRDYH
t
RDYS
(1) 1st data: One internal wait cycle
Information in the first data bus cycle
D31 to D29: Access size
000: Byte
001:
Word (2 bytes)
010: Longword (4 bytes)
011: Quadword (8 bytes)
1xx: Burst (32 bytes)
D25 to D0: Address
(2) 1st data: One internal wait + one external wait cycles
Information in the first data bus cycle
D31 to D29: Access size
000: Byte
001:
Word (2 bytes)
010: Longword (4 bytes)
011: Quadword (8 bytes)
1xx: Burst (32 bytes)
D25 to D0: Address
Legend:
IO: DACK
device
SA: Single-address DMA transfer
DA: Dual-address DMA transfer
Note: DACK is configured as active-high.
Figure 32.20 MPX Basic Bus Cycle (Read)