Renesas SH7781 - Manual (Page 726)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 696 of 1658
REJ09B0261-0100
• DMARS2
Bit Bit Name
Initial
Value R/W Descriptions
15
14
13
12
11
10
C5MID5
C5MID4
C5MID3
C5MID2
C5MID1
C5MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 5 (MID)
See table 14.3.
9
8
C5RID1
C5RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 5 (RID)
See table 14.3.
7
6
5
4
3
2
C4MID5
C4MID4
C4MID3
C4MID2
C4MID1
C4MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 4 (MID)
See table 14.3.
1
0
C4RID1
C4RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 4 (RID)
See table 14.3.