Renesas SH7781 - Manual (Page 820)

17. Power-Down Mode
Rev.1.00 Jan. 10, 2008 Page 790 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
16 to 6
⎯
All 0 R/W Reserved
These bits are always read as 0. The write value
should always be 0.
5, 4 MSTP
[105:104] All 0 R/W Module Stop Bit [105:104]
Specifies that the clock supply to the DMAC channels
of the corresponding bit is stopped
MSTP105: DMAC channels 11 to 6,
MSTP104: DMAC channels 5 to 0
0: DMAC operates
1: DMAC stopped
3 to 1
⎯
All 0 R/W Reserved
These bits are always read as 0. The write value
should always be 0.
0 MSTP100 0 R/W Module Stop Bit 100
Specifies that the clock supply to the GDTA module is
stopped
To stop the clock, set this bit to 1 after confirming that
the operation of GDTA is completed.
0: GDTA operates
1: GDTA stopped
∗
Note: * The GDTA should be placed in module standby state after confirming that the operation
of the GDTA is completed. For the procedure, see section 20.7.1, Regarding Module
Stoppage.