Renesas SH7781 - Manual (Page 1639)

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1609 of 1658
REJ09B0261-0100
32.3.13 SIOF Module Signal Timing
Table 32.18 SIOF Module Signal Timing
Item Symbol Min. Max. Unit Figure
SIOF_MCLK clock input cycle time t
MCYC
t
pcyc
— ns 32.50
SIOF_MCLK input high level width t
MWH
0.4 × t
MCYC
— ns
SIOF_MCLK input low level width t
MWL
0.4 × t
MCYC
— ns
SIOF_SCK clock cycle time t
SICYC
t
pcyc
— ns 32.51 to 32.55
SIOF_SCK output high level width t
SWHO
0.4 × t
SICYC
— ns 32.51 to 32.54
SIOF_SCK output low level width t
SWLO
0.4 × t
SICYC
— ns
SIOF_SYNC output delay time t
FSD
— 10 ns
SIOF_SCK input high level width t
SWHI
0.4 × t
SICYC
— ns 32.55
SIOF_SCK input low level width t
SWLI
0.4 × t
SICYC
— ns
SIOF_SYNC input setup time t
FSS
10 — ns
SIOF_SYNC input hold time t
FSH
10 — ns
SIOF_TXD output delay time t
STDD
— 10 ns 32.51 to 32.55
SIOF_RXD input setup time t
SRDS
10 — ns
SIOF_RXD input hold time T
SRDH
10 — ns
t
MCYC
SIOF_MCLK
t
MWH
t
MWL
Figure 32.50 SIOF_MCLK Input Timing