Renesas SH7781 - Manual (Page 199)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 169 of 1658
REJ09B0261-0100
Figure 7.10 shows a flowchart of a memory access using the ITLB.
Yes
Yes
No
No
No
Yes
Yes
Yes
No
Internal resource access
1
0
1
0
CCR.ICE?
Yes
No
No Yes
No
Instruction access to virtual address (VA)
VA is
in P4 area VA is
in P2 area VA is
in P1 area VA is in P0, U0,
or P3 area
MMUCR.AT = 1
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
VPNs match
and V = 1
VPNs match,
ASIDs match, and
V = 1
Only one
entry matches
SR.MD?
Instruction TLB
multiple hit exception
0 (User)
1 (Privileged)
PR?
C = 1
and CCR.ICE = 1
Cache access
Memory access
(Non-cacheable)
Instruction TLB protection
violation exception
Instruction TLB
miss exception
Hardware ITLB
miss handling
Search UTLB
Match? Record in ITLB
Figure 7.10 Flowchart of Memory Access Using ITLB (TLB Compatible Mode)