Renesas SH7781 - Manual (Page 533)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 503 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
15 to 8
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
7 to 0 LV0TH7 to
LV0TH0 1000 0000 R/W Level 0 Threshold Setting Bits
These bits set the threshold cycles for executing auto-
refresh. The number of cycles is the number of DDR
clock cycles.
When single-unit requests received via the SuperHyway
bus end, auto refresh is given priority over the next
request.
Notes: 1. The TREFI bit value of the DBRFCNT1 register and the LV1TH bit of this register are
added and the result used as the maximum value of the auto-refresh counter, that is,
the maximum interval for refresh commands when periodically issuing auto-refresh
signals. Specify the LV1TH bit value so that the maximum interval is within the
maximum value of the ACT-PRE command interval prescribed in the datasheet of the
respective memory manufacturers. For details, refer to section 12.5.5, Auto-Refresh
Operation.
2. Writing to this register should be performed only when the following condition is met.
When automatic issue of auto-refresh is disabled (when the ARFEN bit in the
DBRFCNT0 register is cleared to 0.).