Renesas SH7781 - Manual (Page 673)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 643 of 1658
REJ09B0261-0100
(3) Accessing PCIC Registers
Configuration Registers: Configuration registers should be read or written with (offset from
configuration register space base address) by configuration accesses. A burst transfer is cut off and
terminated.
Local Registers: Local registers should be accessed with (PCI address + offset) using I/O read or
write commands. Only a single longword access is supported. A burst transfer is cut off and
terminated.
Control Register (PCIECR): The control register space should not be read or written from the
PCI bus using a memory read/write command.
(4)
Access to SH7785
Memory Space: See Section 13.4.4 (1), Accessing Memory Space in This LSI. Areas 0 to 6 (
CS0
to
CS6) on the SH7785 memory map, DDR2-SDRAM space and URAM/ILRAM/OLRAM in the
SH-4A core can be accessed.
On-chip IO Space: The on-chip I/O space should not be read or written from the PCI bus using a
memory read/write command. The read/write operation is not guaranteed.
(5)
Exclusive Access
The lock accessing on the PCI bus is supported.
When the PCI bus is locked, the PCIC is accessible from the device that asserts
LOCK.
Resource lock on the SuperHyway bus is not supported. (Another on-chip module can access the
PCIC during lock transfer.)