Renesas SH7781 - Manual (Page 430)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 400 of 1658
REJ09B0261-0100
(4) Area 3
Area 3 is an area where bits 28 to 26 in the local bus address are 011.
The interface that can be set for this area is the SRAM, MPX, or burst ROM interface.
A bus width of 8, 16, 32, or 64 bits is selectable by bits SZ in CS3BCR. When the MPX interface
is used, a bus width of 32 or 64 bits should be selected by the SZ bits in CS3BCR.
When area 3 is accessed, the
CS3 signal is asserted. When the SRAM interface is set, the RD
signal, which can be used as
OE, and write control signals WE0 to WE7 are asserted.
For the number of bus cycles, 0 to 25 wait cycles inserted can be selected by CS3WCR.
When the burst ROM interface is used, the number of a burst pitch is selectable in the range from
0 to 7 with the BW bits in CS3BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (
RDY).
(when no cycles are inserted, the
RDY signal is ignored.)
The setup/hold time of the address, the assert delay cycle of the read/write strobe signals for
CS3
assertion and the
CS3 negate delay cycle for the read/write strobe signals negation can be set in
the range from 0 to 7 cycles by CS3WCR. The
BS hold cycles can be set to 1 or 2 when the RDS
bits in CS3WCR are not 000 in reading and the WTS bits in CS3WCR are not 000 in writing.
(5)
Area 4
Area 4 is an area where bits 28 to 26 in the local bus address are 100.
The interface that can be set for this area is the SRAM, MPX, byte control RAM, and burst ROM
interface.
A bus width of 8, 16, 32, or 64 bits is selectable by bits SZ in CS4BCR. When the MPX interface
is used, a bus width of 32 bits should be selected through bits SZ in CS4BCR. When the byte
control SRAM interface is used, select a bus width of 16, 32, or 64 bits. For details, see section
11.3.2, Memory Bus Width.
When area 4 is accessed, the
CS4 signal is asserted.
When the SRAM interface is set, the
RD signal, which can be used as OE, and write control
signals
WE0 to WE7 are asserted. For details, see section 11.5.8, Wait Cycles between Access
Cycles.