Renesas SH7781 - Manual (Page 734)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 704 of 1658
REJ09B0261-0100
Table 14.8 List of On-Chip Peripheral Module Request Modes
CHCR DMARS
RS[3:0] MID RID
DMA Transfer
Request Source DMA Transfer Request Signal Source
Destination
Bus
Mode
1000 000000 11 SSI0 transmitter Transmit data empty request
(In transmit mode, the DMRQ
bit in the SSISR0 register is 1.) Any SSITDR0 Cycle
steal
SSI0 receiver Unread data is present (In
receive mode, the DMRQ bit in
the SSISR0 register is 1.) SSIRDR0 Any Cycle
steal
000001 11 SSI1 transmitter Transmit data empty request
(In transmit mode, the DMRQ
bit in the SSISR1 register is 1.) Any SSITDR1 Cycle
steal
SSI1 receiver Unread data is present (In
receive mode, the DMRQ bit in
the SSISR1 register is 1.) SSIRDR1 Any Cycle
steal
001000 01 SCIF0 transmitter TXI (transmit FIFO data empty) Any SCFTDR0 Cycle
steal
10 SCIF0 receiver RXI (receive FIFO data full) SCFRDR0 Any Cycle
steal
001001 01 SCIF1 transmitter TXI (transmit FIFO data empty) Any SCFTDR1 Cycle
steal
10 SCIF1 receiver RXI (receive FIFO data full) SCFRDR1 Any Cycle
steal
001010 01 SCIF2 transmitter TXI (transmit FIFO data empty) Any SCFTDR2 Cycle
steal
10 SCIF2 receiver RXI (receive FIFO data full) SCFRDR2 Any Cycle
steal
001011 01 SCIF3 transmitter TXI (transmit FIFO data empty) Any SCFTDR3 Cycle
steal
10 SCIF3 receiver RXI (receive FIFO data full) SCFRDR3 Any Cycle
steal
001100 01 SCIF4 transmitter TXI (transmit FIFO data empty) Any SCFTDR4 Cycle
steal
10 SCIF4 receiver RXI (receive FIFO data full) SCFRDR4 Any Cycle
steal