Renesas SH7781 - Manual (Page 765)

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 735 of 1658
REJ09B0261-0100
The function of each block in the CPG is as follows.
• PLL circuit 1
PLL circuit 1 multiplies the input clock frequency on the PLL circuit by 36 or 72.
• PLL circuit 2
PLL circuit 2 matches the phases of the bus clock (Bck) and the clock of the CLKOUT pin that
is used in the local bus.
• Crystal oscillator circuit
The crystal oscillator circuit is used when a crystal resonator is connected to the XTAL and
EXTAL pins. The crystal oscillator circuit can be used by the MODE10 pin setting.
For details on input frequency, see section 32, Electrical Characteristics.
• Divider 1
Divider 1 divides the input clock frequency from the crystal oscillator circuit or the EXTAL
pin. The division ratio is set by mode pins MODE3 and MODE4.
• Divider 2
Divider 2 generates the CPU clock (Ick), SuperHyway clock (SHck), GDTA clock (GAck),
DU clock (DUck), peripheral module clock (Pck), DDR clock (DDRck), external bus clock
(Bck), and RAM clock (Uck). The division ratio is selected by mode setting pins MODE0 and
MODE1.