Renesas SH7781 - Manual (Page 572)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 542 of 1658
REJ09B0261-0100
MCK0,
MCK1
MA[14:11]
MA[9:0]
MBA[2:0]
MCKE
MCS
MRAS
MCAS
MWE
MA[10]
Invalid
MDQS[3:0]
MDQ[31:0]
MDM[3:0] Invalid
Invalid
Invalid
Invalid
READ
any
bank
Invalid
Invalid
Invalid
SDRAM
command
Invalid
Invalid
WRITE
any
bank
Write data Read data
WRRD
= 7 cycles
Valid
Valid
Valid
Valid
Valid
Valid
Example of CL= 3
High level
Figure 12.19 WRITE-READ Minimum Time
Figure 12.19 is an example of a case in which, after issuing a WRITE command, a READ
command is issued. In order to issue the READ command after issuing the WRITE command, the
DBSC2 waits for a minimum time stipulated by the WRRD bits.