Renesas SH7781 - Manual (Page 1207)

24. Multimedia Card Interface (MMCIF)
Rev.1.00 Jan. 10, 2008 Page 1177 of 1658
REJ09B0261-0100
24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5)
The CMDR registers are six 8-bit registers. A command is written to CMDR as shown in table
24.4, and the command is transmitted when the CMDSTART bit in CMDSTRT is set to 1. Each
command is transmitted in order form the MSB (bit 7) in CMDR0 to the LSB (bit 0) in CMDR5.
Table 24.4 CMDR Configuration
Register Contents Operation
CMDR0 to
CMDR4 Command argument Write command arguments.
CMDR5 CRC and End bit Setting of CRC is unnecessary (automatic calculation).
End bit is fixed to 1 and its setting is unnecessary
(automatic setting).
The read value is 0.
(1) CMDR0 to CMDR4
Bit:
Initial value:
R/W:
7 6 5 4 3 2 1 0
0 0 0 0
(command argument)
0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W Description
7 to 0 — All 0 R/W Command arguments
See specifications for the MMC card.
Data is sequentially transmitted from CMDR0 MSB to
CMDR5 LSB.