Renesas SH7781 User Manual
Page 314
10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 284 of 1658
REJ09B0261-0100
(5)
Interrupt Mask Register 0 (INTMSK0)
INTMSK0 is a 32-bit readable and conditionally writable register that sets masking for each of the
interrupt requests IRQn (n = 0 to 7). To clear the mask setting for an interrupt, write 1 to the
corresponding bit in INTMSKCLR0. Writing 0 to the bits in INTMSK0 has no effect. By reading
this register once after writing to this register or after clearing the mask by setting
IMTMSKCLR0, the time length necessary for reflecting the register value can be assured (the
value read is reflected to the mask status).
When using IRQ/
IRL3 to IRQ/IRL0 pins or IRQ/IRL7 to IRQ/IRL4 pins for encoded IRL
interrupt inputs, write 1 to IM00 to IM03 or IM04 to IM07, respectively.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
IM07
IM06
IM05
IM04
IM03
IM02
IM00 IM01
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
Bit Name
Initial
Value R/W Description
31
IM00
1
R/W
Sets masking of individual
pin interrupt source on
IRQ0.
30
IM01
1
R/W
Sets masking of individual
pin interrupt source on
IRQ1.
29
IM02
1
R/W
Sets masking of individual
pin interrupt source on
IRQ2.
28
IM03
1
R/W
Sets masking of individual
pin interrupt source on
IRQ3.
[When read]
0: The interrupts are
accepted.
1: The interrupts are
masked.
[When written]
0: No effect
1: Masks the interrupt
27
IM04
1
R/W
Sets masking of individual
pin interrupt source on
IRQ4.