Renesas SH7781 - Manual (Page 369)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 339 of 1658
REJ09B0261-0100
10.5.2 Multiple Interrupts
To handle multiple interrupts, the procedure for the interrupt handling routine should be as
follows.
1. To identify the interrupt source, set the value of INTEVT to an offset and branch it to the
interrupt handling routine for each interrupt source.
2. Clear the corresponding interrupt source in the interrupt handling routine.
3. Save SSR and SPC on the stack.
4. Clear the BL bit in SR. When the INTMU bit in CPUOPM is set to 1, the interrupt mask level
(IMASK) in SR is automatically set to the level of the accepted interrupt. When the INTMU
bit in CPUOPM is cleared to 0, software should be used to set the IMASK bit in SR to the
priority level of the accepted interrupt.
5. Execute processing as required in response to the interrupt.
6. Set the BL bit in SR to 1.
7. Release SSR and SPC from the stack.
8. Execute the RTE instruction.
By following the above procedure, if further interrupts are generated right after step 4, an interrupt
with higher priority than the one currently being handled can be accepted after step 4. This reduces
the interrupt response time for urgent processing.
10.5.3 Interrupt Masking by MAI Bit
When the MAI bit in ICR0 is set to 1, interrupts can be masked whole the NMI pin is low
regardless of the settings of the BL and IMASK bits in and SR.
• Normal operation or sleep mode
All other interrupts are masked while the NMI signal is low. Note that only NMI interrupts due to
the change of the NMI pin are generated.