Renesas SH7781 - Manual (Page 729)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 699 of 1658
REJ09B0261-0100
• DMARS5
Bit Bit Name
Initial
Value R/W Descriptions
15
14
13
12
11
10
C11MID5
C11MID4
C11MID3
C11MID2
C11MID1
C11MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 11 (MID)
See table 14.3.
9
8
C11RID1
C11RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 11 (RID)
See table 14.3.
7
6
5
4
3
2
C10MID5
C10MID4
C10MID3
C10MID2
C10MID1
C10MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 10 (MID)
See table 14.3.
1
0
C10RID1
C10RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 10 (RID)
See table 14.3.