Renesas SH7781 - Manual (Page 507)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 477 of 1658
REJ09B0261-0100
When the external bus width is set to 16 bits
Address 16n + 0
Address 16n + 8
1st access 2nd access
16n + 0 16n + 8
16n + 8 16n + 0
16-byte read/write access (a total of two commands are issued)
Address 32n + 0
Address 32n + 8
Address 32n + 16
Address 32n + 24
1st access 2nd access 3rd access 4th access
32n + 0 32n + 8 32n + 16 32n + 24
32-byte read access (a total of four commands are issued)
32n + 0 32n + 8 32n + 16 32n+ 24
32n + 16 32n + 24 32n + 0 32n + 8
32n + 16 32n + 24 32n + 0 32n + 8
Address 32n + 0
Address 32n + 8
Address 32n + 16
Address 32n + 24
1st access 2nd access 3rd access 4th access
32n + 0 32n + 8 32n + 16 32n + 24
32-byte write access (a total of four commands are issued)
32n + 0 32n + 8 32n + 16 32n + 24
32n + 16 32n + 24 32n + 0 32n + 8
32n + 16 32n + 24 32n + 0 32n + 8
Figure 12.3 Addresses Generated upon 16/32-Byte Access when the External Data Bus
Width Is 16 Bits