8 notes on using 32-bit address extended mode – Renesas SH7781 User Manual
Page 271
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8. Caches
Rev.1.00 Jan. 10, 2008 Page 241 of 1658
REJ09B0261-0100
8.8
Notes on Using 32-Bit Address Extended Mode
In 32-bit address extended mode, the items described in this section are extended as follows.
1. The tag bits [28:10] (19 bits) in the IC and OC are extended to bits [31:10] (22 bits).
2. An instruction which operates the IC (a memory-mapped IC access and writing to the ICI bit
in CCR) should be located in the P1 or P2 area. The cacheable bit (C bit) in the corresponding
entry in the PMB should be 0.
3. Bits [4:2] (3 bits) for the AREA0 bit in QACR0 and the AREA1 bit in QACR1 are extended to
bits [7:2] (6 bits).
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