Renesas SH7781 - Manual (Page 714)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 684 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Descriptions
19 HE 0 R/(W)* Half End Flag
After HIE (bit 18) is set to 1 and the number of transfers
is half of TCR (one bit shift to right) which is set before
transfer, HE is 1.
• HE is set to 1 when the number of transfers is an
even number ((TCR set before transfer)/2)
• HE is set to 1 when the number of transfers is an
odd number ((TCR set before transfer
− 1)/2)
• HE is set to 1 when the number of transfer is the
maximum transfer count 8,388,608 (H'00800000)
The HE bit is not set when transfers are ended by an
NMI interrupt or address error, or by clearing the DE or
DME bit in DMAOR before the number of transfers is
decreased to half of the TCR value set before the
transfer. The HE bit is kept set when the transfer ends
by an NMI interrupt or address error, or clearing the DE
bit (bit 0) or the DME bit in DMAOR after the HE bit is
set to 1. To clear the HE bit, write 0 after reading 1 from
the HE bit. This bit is valid in only CHCR0 to CHCR3,
and CHCR6 to CHCR9.
0: DMA transfer is being performed or DMA transfer has
been aborted TCR
> (TCR set before transfer)/2
Clearing condition: Write 0 after HE is read as 1
1: TCR (TCR set before transfer)/2
18 HIE 0 R/W Half End Interrupt Enable
Specifies whether an interrupt request is generated to
the CPU when the read cycle of the transfer that the
number of transfers is decreased to half of the TCR
value set before the transfer has ended. If the HIE bit is
set to 1, an interrupt request is generated to the CPU
when the HE bit is set. To confirm that the half of the
transfer has ended, execute a dummy read of the
destination space after issuing the SYNCO instruction.
Clear this bit to 0 while reload mode is set. This bit is
valid in CHCR0 to CHCR3, and CHCR6 to CHCR9.
0: Half end interrupt disabled
1: Half end interrupt enabled