Renesas SH7781 User Manual
Page 465
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11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 435 of 1658
REJ09B0261-0100
Tm1
CLKOUT
A
RD/FRAME
CSn
R/
W
D63 to D0
BS
Tmd1
Tmd2
Tmd3
Tmd4
RDY
DACKn
D0
D1
D2
D3
In this example, DACKn is active-high.
Figure 11.30 MPX Interface Timing 7
(Burst Write Cycle, IW
= 0000, No External Wait, 64-Bit Width, 32-Byte Data Transfer)
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