Renesas SH7781 - Manual (Page 698)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 668 of 1658
REJ09B0261-0100
14.3 Register Descriptions
Table 14.2 shows the register configuration.
Table 14.2 Register Configuration of the DMAC (1)
Channel Name Abbrev. R/W P4 Address
Area 7
Address
Access
Size* 3
Sync
clock
0 DMA source address register 0 SAR0 R/W H'FC80 8020 H'1C80 8020 32 Bck
DMA destination address register 0 DAR0 R/W H'FC80 8024 H'1C80 8024 32 Bck
DMA transfer count register 0 TCR0 R/W H'FC80 8028 H'1C80 8028 32 Bck
DMA channel control register 0 CHCR0 R/W* 1 H'FC80 802C H'1C80 802C 32 Bck, Pck* 4
1 DMA source address register 1 SAR1 R/W H'FC80 8030 H'1C80 8030 32 Bck
DMA destination address register 1 DAR1 R/W H'FC80 8034 H'1C80 8034 32 Bck
DMA transfer count register 1 TCR1 R/W H'FC80 8038 H'1C80 8038 32 Bck
DMA channel control register 1 CHCR1 R/W* 1 H'FC80 803C H'1C80 803C 32 Bck, Pck* 4
2 DMA source address register 2 SAR2 R/W H'FC80 8040 H'1C80 8040 32 Bck
DMA destination address register 2 DAR2 R/W H'FC80 8044 H'1C80 8044 32 Bck
DMA transfer count register 2 TCR2 R/W H'FC80 8048 H'1C80 8048 32 Bck
DMA channel control register 2 CHCR2 R/W* 1 H'FC80 804C H'1C80 804C 32 Bck, Pck* 4
3 DMA source address register 3 SAR3 R/W H'FC80 8050 H'1C80 8050 32 Bck
DMA destination address register 3 DAR3 R/W H'FC80 8054 H'1C80 8054 32 Bck
DMA transfer count register 3 TCR3 R/W H'FC80 8058 H'1C80 8058 32 Bck
DMA channel control register 3 CHCR3 R/W* 1 H'FC80 805C H'1C80 805C 32 Bck, Pck* 4
0 to 5 DMA operation register 0 DMAOR0 R/W* 2 H'FC80 8060 H'1C80 8060 16 Bck, Pck* 5
4 DMA source address register 4 SAR4 R/W H'FC80 8070 H'1C80 8070 32 Bck
DMA destination address register 4 DAR4 R/W H'FC80 8074 H'1C80 8074 32 Bck
DMA transfer count register 4 TCR4 R/W H'FC80 8078 H'1C80 8078 32 Bck
DMA channel control register 4 CHCR4 R/W* 1 H'FC80 807C H'1C80 807C 32 Bck, Pck* 4
5 DMA source address register 5 SAR5 R/W H'FC80 8080 H'1C80 8080 32 Bck
DMA destination address register 5 DAR5 R/W H'FC80 8084 H'1C80 8084 32 Bck
DMA transfer count register 5 TCR5 R/W H'FC80 8088 H'1C80 8088 32 Bck
DMA channel control register 5 CHCR5 R/W* 1 H'FC80 808C H'1C80 808C 32 Bck, Pck* 4