Renesas SH7781 - Manual (Page 1375)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1345 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
15 FCKSEL 0 R/W Flash Clock Select
0: Divides the operating clock of the FLCTL (a
peripheral clock) by two and uses it as the FCLK
1: Uses the operating clock of the FLCTL (a peripheral
clock) as the FCLK
14 to 12 — All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
11, 10 ACM[1:0] 00 R/W Access Mode Specification [1:0]
Specify access mode.
00: Command access mode
01: Sector access mode
10: Setting prohibited
11: Setting prohibited
9 NANDWF 0 R/W NAND Wait Insertion Operation
0: No wait
1: A wait cycle is inserted
8 to 4 — All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
3 CE0 0 R/W Chip Enable 0
0: Disabled (Outputs high level to the
FCE pin)
1: Enabled (Outputs low level to the
FCE pin)
2, 1 — All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0 TYPESEL 0 R/W Memory Select
0: Reserved
1: NAND-type flash memory is selected
Note: Set TYPESEL to 1 to use FLCTL.