Renesas SH7781 - Manual (Page 270)

8. Caches
Rev.1.00 Jan. 10, 2008 Page 240 of 1658
REJ09B0261-0100
Physical address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte
boundary.
8.7.4 Determination of SQ Access Exception
Determination of an exception in a write to an SQ or transfer to external memory (PREF
instruction) is performed as follows according to whether the MMU is enabled or disabled. If an
exception occurs during a write to an SQ, the SQ contents before the write are retained. If an
exception occurs in a data transfer from an SQ to external memory, the transfer to external
memory will be aborted.
• When MMU is enabled (AT = 1 in MMUCR)
Operation is in accordance with the address translation information recorded in the UTLB, and
the SQMD bit in MMUCR. Write type exception judgment is performed for writes to the SQs,
and read type exception judgment for transfer from the SQs to external memory (using a PREF
instruction). As a result, a TLB miss exception or protection violation exception is generated
as required. However, if SQ access is enabled in privileged mode only by the SQMD bit in
MMUCR, an address error will occur even if address translation is successful in user mode.
• When MMU is disabled (AT = 0 in MMUCR)
Operation is in accordance with the SQMD bit in MMUCR.
0: Privileged/user mode access possible
1: Privileged mode access possible
If the SQ area is accessed in user mode when the SQMD bit in MMUCR is set to 1, an address
error will occur.
8.7.5 Reading from SQ
In privileged mode in this LSI, reading the contents of the SQs may be performed by means of a
load instruction for addresses H'FF00 1000 to H'FF00 103C in the P4 area. Only longword access
is possible.
[31:6] : H'FF00 1000 Store queue specification
[5] : 0/1 0: SQ0 specification
1: SQ1 specification
[4:2] : LW specification Specifies longword position in SQ0/SQ1
[1:0] : 00 Fixed at 0