1 memory address map select register (mmselr) – Renesas SH7781 User Manual
Page 394
11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 364 of 1658
REJ09B0261-0100
11.4.1
Memory Address Map Select Register (MMSELR)
MMSELR is a 32-bit register that selects memory address maps for areas 2 to 5. This register
should be accessed at the address H'FC40 0020 in longword. To prevent incorrect writing, writing
is accepted only when the upper 16-bit data is H'A5A5. The upper 29 bits are always read as 0.
This register is initialized to H'0000 0000 by a power-on reset or a manual reset.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AREASEL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
BIt:
Initial value:
R/W:
Code for writing (H'A5A5)
Bit Bit
Name
Initial
Value R/W Description
31 to 16 (Code for
writing)
All 0
R/W
Code for writing
Set these bits to H'A5A5 (write H'A5A5 to these bits)
when writing to AREASEL (bits 2 to 0) in this register.
These bits are always read as 0.
15 to 3
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.