Renesas SH7781 - Manual (Page 1297)

25. Audio Codec Interface (HAC)
Rev.1.00 Jan. 10, 2008 Page 1267 of 1658
REJ09B0261-0100
Table 25.2 Register Configuration (2)
Channel Register Name Abbrev.
Power-on
Reset by
PRESET
Pin/WDT/
H-UDI Manual
Reset by
WDT/
Multiple
Exceptions
Sleep by
Sleep
Instruction
Module
Standby Deep
Sleep
0 Control and status
register 0
HACCR0 H'0000 0200 H'0000 0200 Retained Retained Retained
0 Command/status
address register 0
HACCSAR0 H'0000 0000 H'0000 0000 Retained Retained Retained
0 Command/status
data register 0
HACCSDR0 H'0000 0000 H'0000 0000 Retained Retained Retained
0 PCM left channel
register 0 HACPCML0 H'0000 0000 H'0000 0000 Retained Retained Retained
0 PCM right channel
register 0 HACPCMR0 H'0000 0000 H'0000 0000 Retained Retained Retained
0 TX interrupt enable
register 0 HACTIER0 H'0000 0000 H'0000 0000 Retained Retained Retained
0 TX status register
0
HACTSR0 H'F000 0000 H'F000 0000 Retained Retained Retained
0 RX interrupt
enable register 0
HACRIER0 H'0000 0000 H'0000 0000 Retained Retained Retained
0 RX status register
0 HACRSR0 H'0000 0000 H'0000 0000 Retained Retained Retained
0 HAC control
register 0
HACACR0 H'8400 0000 H'8400 0000 Retained Retained Retained