Renesas SH7781 - Manual (Page 481)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 451 of 1658
REJ09B0261-0100
11.5.11 Slave Mode
In slave mode, usually, the bus is released. Unless the bus control is hold by performing bus
arbitration, the external device cannot be accessed. The bus is released at a reset, and the bus
arbitration sequence starts from the fetch of the reset vector.
To get the bus mastership, the
BSREQ signal is asserted (driven low) in synchronous with the
rising edge of the clock. The
BSACK signal, a bus use permission signal, is sampled at the rising
edge of the clock. When the asserted
BSACK is detected, the bus control signal is driven low at
negate level after two cycles. At the following rising edge of the clock, the bus cycle starts. The
signal negated last at the end of the access cycle is synchronized with the rising edge of the clock.
As soon as the bus cycle ends, the
BSREQ signal is negated to notify the master that the bus is
released. At the next rising edge of the clock, the control signal is put in high-impedance.
If the processor in slave mode starts access, two or more cycles of
BSACK signal assertion are
required.
11.5.12
Cooperation between Master and Slave
To control system resources without contradiction by the master and slave, their respective roles
must be clearly defined, as well as in the standby state implementing power-down mode.
The design of the SH7785 provides for all control, including initialization, and standby control, to
be carried out by the master mode device.
If the SH7785 is specified as the master at a power-on reset, it will not accept bus requests from
the slave until the
BREQ enable bit (BREQEN in BCR) is set to 1.
To ensure that the slave processor does not access memory requiring initialization before
completion of initialization, write 1 to the
BREQ enable bit after the initialization is complete.
11.5.13 Power-Down Mode and Bus Arbitration
When deep sleep mode is used, in the system that performs bus arbitration, the BREQEN bit in
BCR of the processor in master mode should be cleared to 0 before a transition is made to deep
sleep mode. If a transition is made to deep sleep mode when the bit is set to 1, the operation is not
guaranteed.