Figure 4.2 instruction execution patterns (6) – Renesas SH7781 User Manual
Page 102
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4. Pipelining
Rev.1.00 Jan. 10, 2008 Page 72 of 1658
REJ09B0261-0100
I1
I2
I3
ID
s1
s2
s3
WB
MS
I3
I3
I3
I3
I3
I3
I3
I3
I1
I2
ID
E1
M2
M3
E1
M2
M3
MS
E1
M2
M3
MS
M2
M3
MS
I1
I2
ID
I1
I2
ID
S1
S2
S3
WB
S1
S2
S3
WB
I1
I2
ID
I1
I2
ID
s1
s2
s3
WB
MS
I1
I2
ID
S1
S2
S3
WB
MS
I1
I2
ID
S1
S2
S3
WB
MS
M2
M3
MS
M2
M3
MS
M2
M3
I1
I2
ID
S1
S2
S3
WB
S1
S2
S3
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ID
ID
(5-1) LDS to MACH/L: 1 issue cycle
(5-2) LDS.L to MACH/L: 1 issue cycle
(5-3) STS from MACH/L: 1 issue cycle
(5-4) STS.L from MACH/L: 1 issue cycle
(5-5) MULS.W, MULU.W: 1 issue cycle
(5-6) DMULS.L, DMULU.L, MUL.L: 1 issue cycle
(5-7) CLRMAC: 1 issue cycle
(5-8) MAC.W: 2 issue cycle
(5-9) MAC.L: 2 issue cycle
Figure 4.2 Instruction Execution Patterns (6)
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