Renesas SH7781 - Manual (Page 319)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 289 of 1658
REJ09B0261-0100
Bit Name
Initial
Value R/W Description
15 IM115 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = LLLL
(H'0).
14 IM114 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = LLLH
(H'1).
13 IM113 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = LLHL
(H'2).
12 IM112 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = LLHH
(H'3).
[When read]
0: The interrupt is
accepted.
1: The interrupt is
masked.
[When written]
0: No effect
1: Masks the interrupt
11 IM111 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = LHLL
(H'4).
10 IM110 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = LHLH
(H'5).
9 IM109 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = LHHL
(H'6).
8 IM108 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = LHHH
(H'7).
7 IM107 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = HLLL
(H'8).
6 IM106 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = HLLH
(H'9).
5 IM105 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = HLHL
(H'A).
4 IM104 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = HLHH
(H'B).
3 IM103 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = HHLL
(H'C).